1. Field of the Invention
The present invention relates to a data transfer interface mounted on a system LSI, and more particularly to a data transfer system including a semiconductor memory device having an ultrahigh-speed data transfer interface between LSIs.
2. Description of the Background Art
For example, Japanese Patent Laying-Open No. 5-342118 discloses a conventional technique of increasing information transfer efficiency.
According to a data communication method of the conventional technique, information of different attributes is transmitted/received by a synchronous communication system or an asynchronous communication system. By selecting a communication system at the time of transmission in accordance with the attributes of information transmitted/received, information is transmitted/received according to a method adapted to the attributes of the information. By performing transmission and reception of information via independent paths, information transfer efficiency is increased.
Japanese Patent Laying-Open Nos. 4-331521 and 7-311735 disclose conventional techniques realizing high-speed data transfer by performing phase adjustment in correspondence with each of a plurality of units and devices.
Conventionally, in the case of performing data transfer used for a system LSI, when one path for transmitting data signals includes a plurality of signal lines, the phases of signals have to be aligned in the plurality of signal lines. Consequently, phases which can be adjusted are constrained due to variations in impedances of the signal lines and the upper limit of the operation frequency is determined accordingly. In the case of using a nonvolatile memory as a memory connected to a high-speed data transfer interface, in a control system using an EEPROM and a flash memory, it takes time to program the memories. In this case, at the time of reading information while being downloaded from a server via a network, a dedicated buffer memory is necessary and transfer speed in a network is considerably regulated.